1. Field of the Invention
The present invention pertains to integrated circuit devices, and more particularly to semiconductor read only memories.
2. Description of the Prior Art
Continuing efforts in the prior art have been directed to the miniaturization of integrated circuit devices. One such integrated circuit device is a read only memory (ROM), which has recently been miniaturized to the point where a single memory bit measures approximately 196 square microns, as reported in the IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 3,6/76, p. 360-364.
FIG. 1 illustrates such a prior art ROM 10, which comprises: a substrate 12 of N-type silicon, conductive layers 14 of polycrystalline silicon ("polysilicon") insulated from the substrate 12 by oxide layers 16, and a protective coating 18 of phosphorus stabilized glass covering the layers 14 and 16 and the substrate surfaces therebetween. Heavily doped regions 20, which are formed by P-type diffusion, are disposed in portions of substrate 12 not covered by layers 14 and 16.
The ROM 10 comprises a series string 22 of P-channel field-effect transistors as illustrated in FIG. 2. The P.sup.+ regions 20 provide common source (S) and drain (D) connections between adjacent transistors. The polysilicon layers 14 provide gate (G) electrodes. Selected transistors operate in the depletion mode (DM), while the remaining transistors operate in the enhancement mode (EM). The depletion-mode transistors have ion-implanted channels 24 of P-type conductivity, as shown in FIG. 1.
Binary information is coded in the ROM 10 in the form of the mode type of each transistor, (e.g., depletion mode represents a stored "0"; enhancement mode represents a stored "1"). In order to interrogate a selected transistor to determine its mode type, the impedance of the series string 22 is monitored at V.sub.out while all but the selected transistor are caused to conduct. In particular, the gates of the nonselected transistors are held "high", (which is a negative voltage for a P-channel FET, e.g., minus 12 volts). The gate of the selected transistor is caused to go "low" (typically near ground potential). Then a clock pulse causes a reference voltage (V.sub.ref) to be applied to the series string 22. It an then be determined by the potential at V.sub.out whether the selected transistor is conducting (i.e. depletion mode) or nonconducting (i.e. enhancement mode).
A two-dimensional matrix is readily formed using the above techniques by arranging series strings of active transistor regions in parallel columns, wherein transversely running rows of polysilicon layers form common gate electrodes for correspondingly located transistors in each column.